A memory device is having at least one input line(s) to specify a next status to be, and having at least one output line(s) to know what kind of status it is now in. This definition can be applied to random access memory with arrangement of semiconductor memory devices in the form of matrix, as well as, widely to sequential access memory such as magnetic disk, magnetic drum, magnetic tape and the like. Hereinafter, there is illustrated, for example, a RS flip flop of matrix arrangement as a representative of memory device.
FIG. 1 shows a basic structure of the prior art memory device.
Where memory 1 comprises, for example, of 4.times.4 bit memory cells, two bits of lower-order position among the four bits of address signals are used for X decoder 2 to specify the position in X coordinate, selecting from 2.times.2=4 positions, and two bits of the higher-order position are used for Y-decoder 3 to specify the position in Y-coordinate, selecting from 4 positions, thereby to select the memory cell at the location determined by X-position and Y-position. Simultaneously, the instruction of reading(R) or writing(W) is set. In case of writing(W), data to be written enters(DATA in). In case of reading, data to be read is picked out(DATA out). Consequently, the conventional memory can address only one cell at the same time, and therefore, only one cell among 4.times.4 bit memory cells can be accessed to read or write. As usual, in memory called "dual port memory" with connection to two buses, address is instructed independently from the two buses, but in this device the two address signals are rearranged in time series signal to access into the memory cells, and therefore, it is not simultaneous access, but only serial access.
FIG. 2 shows the internal structure of the memory of FIG. 1.
The prior art 4.times.4 bit memory is as shown in FIG. 2 comprised of sixteen memory cells 11, each of which 11 is connected to each one of address lines(0-3) in Y coordinate and one of address lines in X coordinate, as well as, to input/output data lines. As shown in FIG. 2, signal of read/write control line allows output of input/output data line valid in case of reading, and allows the input valid in case of writing. In each of the memory cells 11, the commands of X address and Y address are applied to AND gate 13, thereby, the output "1" signal activates the flip-flop 12, at the same time, the signal representing set or reset status of the addressed cell is fetched out, or the signal to set or reset status of the addressed cell is put into the memory cell, depending on read or write instructions.
FIG. 3 is a logical diagram of flip-flop content of FIG. 2.
As described above, X address signal and Y address signal are applied to AND gate, and when this flip-flop 12 is selected, "1" output is sent from AND gate 13 to NAND gates 14 and 15 of the flip-flop 12. NAND gates 16 and 17 make a latch circuit and the input stage for writing data in NAND gate 14 and 15, and the output stage for reading data in AND gate 18 are connected respectively to before and after stage of latch circuit.
On the other hand, in case of reading, input/output data lines functions as an output line by instructing to read, so that input signal(DATA IN) is cut off, and output signal(DATA OUT) will be "1" or "0", depending on the stored data in memory cell. In case of writing, input/output data lines functions as an input line where it instructs to read. Therefore, input signal(DATA IN) is "1" or "0" to be written. Output signal(DATA OUT) is the stored data which has been written, but it is not fetched through the input/output data line, thereby to cut off signal. Therefore, the operation of flip-flop 12 is as follows;
When not-selected: PA0 When written: PA0 When read:
"1" gate 14 output "1" gate 16 output "1". PA1 "1" gate 15 output "1" gate 17 output "0". PA1 "0" gate 14 output "1" gate 16 output "0". PA1 "0" gate 15 output "1" gate 17 output "1". PA1 "1" gate 14 output "0" gate 16 output "1". PA1 "1" gate 15 output "1" gate 17 output "0". PA1 "0" gate 14 output "1" gate 16 output "0". PA1 "0" gate 15 output "0" gate 17 output "1". PA1 "1" gate 14 output "1" gate 16 output "1". PA1 "1" gate 15 output "1" gate 17 output "0". PA1 "0" gate 14 output "1" gate 16 output "0". PA1 "0" gate 15 output "1" gate 17 output "1".
In the above mentioned prior art memory, even when requests for access rush in, actually only one request can be satisfied to access at the same time, so that processing time can not be lowered. Furthermore, where memory is used alternatively and independently for CPU or I/O device, the fact is that if one is occupied, the other is waiting, and therefore, the efficiency of utility can not increase.
The object of the present invention is to remove such defects of the prior art device, by multiple simultaneous parallel access to enable multiple processing of memory, and high speed transfer of data, and further to provide a multiple simultaneous access memory to allow independent buffer-transfer by input/output device on CPU processing.